FRDE=0, WSF=0, FWIE=0, DBGE=0, FEF=0, SEIE=0, WSIE=0, STOPE=0, RE=0, BCE=0, FEIE=0, FRF=0, FR=0, SEF=0, FWF=0, FRIE=0, SR=0, FWDE=0
SAI Receive Control Register
| FRDE | FIFO Request DMA Enable 0 (0): Disables the DMA request. 1 (1): Enables the DMA request. |
| FWDE | FIFO Warning DMA Enable 0 (0): Disables the DMA request. 1 (1): Enables the DMA request. |
| FRIE | FIFO Request Interrupt Enable 0 (0): Disables the interrupt. 1 (1): Enables the interrupt. |
| FWIE | FIFO Warning Interrupt Enable 0 (0): Disables the interrupt. 1 (1): Enables the interrupt. |
| FEIE | FIFO Error Interrupt Enable 0 (0): Disables the interrupt. 1 (1): Enables the interrupt. |
| SEIE | Sync Error Interrupt Enable 0 (0): Disables interrupt. 1 (1): Enables interrupt. |
| WSIE | Word Start Interrupt Enable 0 (0): Disables interrupt. 1 (1): Enables interrupt. |
| FRF | FIFO Request Flag 0 (0): Receive FIFO watermark not reached. 1 (1): Receive FIFO watermark has been reached. |
| FWF | FIFO Warning Flag 0 (0): No enabled receive FIFO is full. 1 (1): Enabled receive FIFO is full. |
| FEF | FIFO Error Flag 0 (0): Receive overflow not detected. 1 (1): Receive overflow detected. |
| SEF | Sync Error Flag 0 (0): Sync error not detected. 1 (1): Frame sync error detected. |
| WSF | Word Start Flag 0 (0): Start of word not detected. 1 (1): Start of word detected. |
| SR | Software Reset 0 (0): No effect. 1 (1): Software reset. |
| FR | FIFO Reset 0 (0): No effect. 1 (1): FIFO reset. |
| BCE | Bit Clock Enable 0 (0): Receive bit clock is disabled. 1 (1): Receive bit clock is enabled. |
| DBGE | Debug Enable 0 (0): Receiver is disabled in Debug mode, after completing the current frame. 1 (1): Receiver is enabled in Debug mode. |
| STOPE | Stop Enable 0 (0): Receiver disabled in Stop mode. 1 (1): Receiver enabled in Stop mode. |
| RE | Receiver Enable 0 (0): Receiver is disabled. 1 (1): Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. |